1. Field of Use
This invention pertains to apparatus for resolving access to an asynchronous bus on a priority basis. More particularly, it pertains to resolving priorities between a plurality of intra or local requestors for access to the asynchronous bus shared by a plurality of inter or external requestors.
2. Prior Art
There are several U.S. patents of this inventor for a distributed tie-breaking network included in an asynchronous bus system of the type found in the present invention. These include U.S. Pat. No. 4,096,569 which issued on June 20, 1978 and U.S. Pat. No. 4,559,595 which issued on Dec. 17, 1985.
U.S. Pat. No. 4,096,569, the priority logic circuits of the distributed tie-breaking network grants bus cycles and resolves simultaneous requests to use the bus on the basis of a unit's physical position on the bus with the lowest priority being given to the last unit on the bus located at the opposite end of the bus. U.S. Pat. No. 4,559,595 discloses an improvement to the priority logic circuits of U.S. Pat. No. 4,096,569. The priority logic circuits are modified to allow the lowest priority (i.e., the last unit) to be physically at other than its lowest priority position.
Additionally, there are several patents and patent applications of the same assignee which disclose arrangements for resolving the allocation of a shared resource on a priority basis. These include U.S. Pat. No. 4,493,036 invented by Daniel A. Boudreau and Edward R. Salas which issued on Jan. 8, 1985, U.S. Pat. No. 4,600,992 which issued on July 15, 1986 and the copending patent application of Richard A. Lemay entitled, "Tandem Priority Resolver" bearing Ser. No. 07/030,328, filed on Mar. 26, 1987.
In U.S. Pat. Nos. 4,493,036 and 4,600,992, priority resolver logic circuits are provided within a main memory to resolve possible conflicts between competing requests for access to memory. The patent discloses priority resolver logic in which the lowest priority requestor has the shortest logical path through the resolver logic. The patent teaches that in a priority resolver, it is also desirable, particularly when resolving competing requests for access to main memory to be able to initiate a cycle as early as possible even before the final resolution as to which one of the completing requests will be granted access to the shared resource. This is accomplished by ORing together all of the outputs of the requestors grant flip-flops, each of which is set at the beginning of each priority resolution cycle when the associated requestor has requested use of the shared resource. The signal resulting from such ORing provides an early shared resource initiate signal that indicates that at least one priority level has requested use of the shared resource even though the final winner has not yet been determined. This signal is used to initiate a cycle within the shared resource even before the final priority winner is determined.
U.S. Pat. No. 4,493,036 discloses a priority resolver which is similar to that of U.S. Pat. No. 4,600,992. Additionally, the disclosed priority resolver provides for the dynamic adjustment of the priority level among competing requests as conditions require.
In the case of both U.S. Pat. Nos. 4,493,036 and 4,600,992, the priority logic circuits for resolving the allocation of the shared memory resource on a priority basis are used in addition to the priority network which is used to resolve completing requests for use of the system's common bus. What this has meant is that the priority resolution of competing requests for access to the common bus which can be viewed as a resource external to the system and the priority resolution of competing requests by internal to the system have proceeded in tandem or in series.
More specifically, a similar approach to ORing internal competing requests for use of the common bus has been used to generate a type of early shared resource signal. This signal was then used to initiate a bus cycle before the completion of the resolution cycle. However, only after the bus has been won or access has been granted is the priority resolution of competing requests from units internal to the system (e.g. units located on the same board) has been allowed to take place.
This separate treatment of resolving competing requests from internal requestors and external requestors has increased the time required for granting access to a common bus in systems in which both external and internal requestors must compete for access to such common bus. The total access time has been the sum of both priority resolution cycles.
The above referenced Lemay copending patent application discloses an arrangement for reducing the amount of time for resolving competing requests performed in priority resolution circuits in a serial fashion. This is accomplished by including means in a first priority resolver circuit associated with an adapter which generates an initial access request signal as an input to a second priority resolver circuit associated with a memory before the first circuit has decided which source has been granted access.
The patent application discloses that the arrangement of Lemay can also be used in resolving competing requests for access to the system bus via an adapter. This means that a priority resolver circuit similar to the second priority resolver circuit is used to combine the requests received from the local requestors into a single request signal. This request signal is forwarded to the system bus while the resolver circuit decides which local requestor was to be granted priority when it was established by the bus priority resolver circuit that the adapter has been granted access to the system bus.
While the arrangement in Lemay decreases the amount of time for resolving requests required to be passed through both priority resolver circuits, there is still a finite amount of time required to be expended in partially resolving requests first on a local or internal level prior to initiating the request for system bus access. The total time in this system calculates to be approximately one-half of the local resolution cycle and the bus resolution cycle. Furthermore, the Lemay arrangement for resolving priorities of competing local requests is not easily expanded in terms of the number of requestors.
The above disadvantages in terms of speed and expandability result in reduced system performance and increased complexity. This is particularly true in those computer organizations which are required to service requests from a plurality of units which connect in common to a high speed local bus. In such instances, delays in accessing the system bus become cumulative resulting in substantial decreases in system performance.
Accordingly, it is a primary object of the present invention to provide an improved priority resolver for resolving priorities between competing internal or local requests for granting access to an external resource on the basis of the requestor's physical position on the bus relative to other competing requestors which connect to the bus.
It is a more specific object of the present invention to provide an arrangement for resolving competing requests for use of an asynchronous bus from both local and external requestors within a minimum of time.